Synopsis - Jan 20, 2012
Solicitation Number: N/A
Reference Number: TTO0952
Posted Date: Jan 20, 2012
FedBizOpps Posted Date: Jan 20, 2012
Recovery and Reinvestment Act Action: No
Original Response Date: Jun 01, 2012
Current Response Date: Jun 01, 2012
Classification Code: 99 -- Miscellaneous
NAICS Code: 927110
Contracting Office Address
NASA/Langley Research Center, Mail Stop 12, Industry Assistance Office, Hampton, VA 23681-0001
NASA Langley Research Center in Hampton, VA solicits interest from companies interested in obtaining license rights to commercialize, manufacture and market the following technology. License rights may be issued on an exclusive or nonexclusive basis and may include specific fields of use.
NASA Langley has developed a firmware approach to mitigating single event upsets (SEUs) in radiation-tolerant field programmable gate arrays (FPGAs), including configuration memory, clock management, and configuration logic. Since this technology can be implemented within an FPGA, there is no need for the additional external hardware currently required for SEU mitigation, thus lowering cost, weight, and power; decreasing complexity; and improving reliability. NASA Langley has developed the technology for high-performance space-based computing applications. The technology has been tested and will be used on an instrument on NASA's Mars Science Laboratory rover, scheduled for launch in 2009.
NASA developed the technology to meet the needs for on-board satellite data processing for future missions. The continuing trends toward ever-increasing resolution, improved data quality, and additional capacity for raw and/or processed data will necessitate the use of larger on-board memories, which must be made radiation tolerant. This technology is a firmware approach to radiation-tolerant memory, suitable for both GEO and LEO missions.
Memory cells in FPGAs are susceptible to SEUs. It is important to correct configuration memory upset as quickly as possible. NASA has used an approach of refreshing the configuration memory cells at regular intervals. The configuration bit stream is stored in memory and upon power-on, the FPGA loads its configuration from memory. The memory refresh controller is implemented internally in the FPGA. The correction of SEUs in configuration logic requires initial detection of a failure in configuration logic, which has also been developed and incorporated as part of this technology.
In addition to detecting SEUs, the technology implements a scrubbing strategy where the memory contents are read sequentially and when an error is detected, the memory is updated with correct data.
To express interest in this opportunity, please respond to Sean Sullivan, Research Triangle International (RTI), at: NASA Langley Research Center, Strategic Relationships Office (SRSO), 17 West Taylor St., Mail Stop 218, Building 1212, Room 110 Hampton, Virginia, E-mail: Sean.D.Sullivan@NASA.gov, or phone: 757-864-5055. Please indicate the date and title of the FBO notice and include your company and contact information.
RTI is responsible for aggregating and acknowledging all responses. These responses are provided to members of NASA Langley's Innovative Partnerships Office within the SRO for the purpose of promoting public awareness of our technology products, and conducting preliminary market research to determine public interest in and potential for future licensing opportunities. If direct licensing interest results from this posting, SRO will follow the formal licensing process of posting in the Federal Register as required. No follow-on procurement is expected to result from responses to this Notice.
Point of Contact
Name: Sean Sullivan
Title: Media Specialist
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